| 8:45AM-9:00AM |
Introductions
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Hot Chips 34 Welcome
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| 9:00AM-11:00AM |
GPUs & HPC Chair: Natalia Vassilieva, Cerebras |
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NVIDIA’s Hopper GPU: Scaling Performance
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Jack Choquette & Ronny Krashinsky, NVIDIA |
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AMD Instinct™ MI200 Series Accelerator and Node Architectures
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Alan Smith & Norman James, AMD |
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Intel’s Ponte Vecchio GPU: Architecture, System and Software
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Hong Jiang, Intel |
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Biren BR100 GPGPU: Accelerating Datacenter Scale AI Computing
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Mike Hong & Lingjie Xu, Biren Technology |
| 11:00AM-11:30AM |
Break
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| 11:30AM-12:00PM |
Integration Technologies (part1) Chair: Pradeep Dubey, Intel |
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Passage—A Wafer-Scale, Programmable Photonic Communication Substrate
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Nicholas Harris, Lightmatter |
| 12:00PM-1:00PM |
Break
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| 1:00PM-2:00PM |
Keynote #1 Chair: Krste Asanovic, UC Berkeley/SiFive |
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Semiconductors Run the World
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Pat Gelsinger, Intel |
| 2:00M-3:30PM |
Integration Technologies (part2) Chair: Pradeep Dubey, Intel |
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Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF Applications
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Sergey Yuryevich Shumarayev, Intel |
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Enabling scalable application-specific optical engines (ASOE) by monolithic integration of photonics and electronics
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Christoph Schulien, Ranovus |
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Scaling of Memory Performance and Capacity with CXL Memory Expander
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Sung Joo Park, Samsung |
| 3:30PM-4:00PM |
Break
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| 4:00PM-6:00PM |
Academia Chair: Forest Baskett, NEA |
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HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces
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Abhishek Bhattacharjee & Rajit Manohar, Yale University |
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Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs
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Alfio Di Mauro, ETH Zurich |
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Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration
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Kathleen Feng, Stanford |
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Arm Morello Evaluation Platform - Validating CHERI-based Security in a High-performance System
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Richard Grisenthwaite, Arm |