Hot Chips 34 has concluded. Thank you to the speakers, attendees, sponsors, press, and volunteers!

latest program zipfile

Tutorials: Sunday, August 21, 2022

Time (PDT) Title Presenters
9:00AM-12:30PM CXL

Chair: Nathan Kalyanasundharam, CXL Board & AMD
 
9:00AM-10:00AM CXL overview and evolution
Ishwar Agarwal, Intel
10:00AM-11:00AM CXL2/CXL3 coherency deep dive
Robert Blankenship, Intel
11:00AM-11:45AM Memory use cases and challenges
Prakash Chauhan & Mahesh Wagh, Meta & AMD
11:45AM-12:30PM CXL3 Fabric introduction & use cases
Tony Brewer & Nathan Kalyanasundharam, Micron & AMD
12:30PM-1:30PM Break (1 hr)
 
1:30PM-5:00PM Heterogeneous Compilation in MLIR

Chair: Stephen Neuendorffer, AMD
 
  Intro
Stephen Neuendorffer, AMD
1:30PM-2:15PM Basic Concepts
Jacques Pienaar, Google
2:15PM-3:10PM Code Generation
Harsh Menon, Nod.AI
3:10PM-4:05PM ML Frontends and frameworks
Suraj Sudhir, Arm
4:05PM-5:00PM CIRCT
Andrew Lenharth & John Demme, SiFive & Microsoft

Conference Day 1: Monday, August 22, 2022

Time (PDT) Title Presenters
8:45AM-9:00AM Introductions
 
  Hot Chips 34 Welcome
 
9:00AM-11:00AM GPUs & HPC

Chair: Natalia Vassilieva, Cerebras
 
  NVIDIA’s Hopper GPU: Scaling Performance
Jack Choquette & Ronny Krashinsky, NVIDIA
  AMD Instinct™ MI200 Series Accelerator and Node Architectures
Alan Smith & Norman James, AMD
  Intel’s Ponte Vecchio GPU: Architecture, System and Software
Hong Jiang, Intel
  Biren BR100 GPGPU: Accelerating Datacenter Scale AI Computing
Mike Hong & Lingjie Xu, Biren Technology
11:00AM-11:30AM Break
 
11:30AM-12:00PM Integration Technologies (part1)

Chair: Pradeep Dubey, Intel
 
  Passage—A Wafer-Scale, Programmable Photonic Communication Substrate
Nicholas Harris, Lightmatter
12:00PM-1:00PM Break
 
1:00PM-2:00PM Keynote #1

Chair: Krste Asanovic, UC Berkeley/SiFive
 
  Semiconductors Run the World
Pat Gelsinger, Intel
2:00M-3:30PM Integration Technologies (part2)

Chair: Pradeep Dubey, Intel
 
  Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF Applications
Sergey Yuryevich Shumarayev, Intel
  Enabling scalable application-specific optical engines (ASOE) by monolithic integration of photonics and electronics
Christoph Schulien, Ranovus
  Scaling of Memory Performance and Capacity with CXL Memory Expander
Sung Joo Park, Samsung
3:30PM-4:00PM Break
 
4:00PM-6:00PM Academia

Chair: Forest Baskett, NEA
 
  HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces
Abhishek Bhattacharjee & Rajit Manohar, Yale University
  Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs
Alfio Di Mauro, ETH Zurich
  Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration
Kathleen Feng, Stanford
  Arm Morello Evaluation Platform - Validating CHERI-based Security in a High-performance System
Richard Grisenthwaite, Arm

Conference Day 2: Tuesday, August 23, 2022

Time (PDT) Title Presenters
8:30AM-11:00AM Machine Learning

Chair: Ronny Krashinsky, NVIDIA
 
  Groq Software-Defined Scale-out Tensor Streaming Multi-Processor
Dennis Abts, Groq
  Boqueria - Next Generation At-Memory Inference Acceleration Device with 1,000+ RISC-V cores
Robert Beachler, Untether AI
  DOJO: The Microarchitecture of Tesla’s Exa-Scale Computer
Emil Talpes, Tesla
  DOJO - Super-Compute System Scaling for ML Training
Bill Chang, Tesla
  Cerebras Architecture Deep Dive: First Look Inside the HW/SW Co-Design for Deep Learning
Sean Lie, Cerebras
11:00AM-11:30AM Break
 
11:30AM-1:00PM Network and Switches

Chair: Mark Hill, Microsoft/UW-Madison
 
  AMD 400G Adaptive SmartNIC SOC
Jaideep Dastidar, AMD
  Juniper’s Express 5: A 28.8Tbps Network Routing ASIC and Variations
Chang-Hong Wu, Juniper
  NVLink-Network Switch - NVIDIA’s Switch Chip for High Communication-Bandwidth SuperPODs
Alexander Ishii and Ryan Wells, NVIDIA
1:00PM-2:00PM Break
 
2:00PM-3:00PM Keynote #2

Chair: Ron Diamant, Amazon
 
  Beyond Compute - Enabling AI through System Integration
Ganesh Venkataramanan, Tesla Motors
3:00PM-4:30PM ADAS and Grace

Chair: Ian Bratt, Arm
 
  NVIDIA’s Orin System-on-Chip
Michael Ditty, NVIDIA
  NODAR 3D Vision System: Enabling Mass Production of Autonomous Vehicles
Leaf Jiang, NODAR
  NVIDIA’s Grace CPU
Jonathon Evans, NVIDIA
4:30PM-5:00PM Break
 
5:00PM-7:00PM Mobile & Edge Processors

Chair: Debjit Das Sarma, Tesla
 
  AMD Ryzen 6000 Series Processor
Jim Gibney, AMD
  Meteor Lake and Arrow Lake : Intel Next Gen 3D Client Architecture Platform with Foveros
Wilfred Gomes, Intel
  Dimensity 9000 – A Flagship SmartPhone SoC
Ericbill Wang, MediaTek
  Next-Generation Intel processor build for the edge - Intel Xeon D 2700 & 1700
Praveen Mosur, Intel
7:00PM-7:15PM HC34 Closing
 
  Hotchips Closing Remarks
 

Posters

(NOTE: Not all posters have videos)

Title Authors & Affiliation
DSPU: A 281.6mW Real-Time Deep Learning-Based Dense RGB-D Data Acquisition with Sensor Fusion and 3D Perception System-on-Chip Dongseok Im, Gwangtae Park, Zhiyong Li, Junha Ryu, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon and Hoi-Jun Yoo; KAIST
HNPU-V2: A 46.6 FPS DNN Training Processor for Real-World Environmental Adaptation based Robust Object Detection on Mobile Devices Donghyeon Han, Dongseok Im, Gwangtae Park, Youngwoo Kim, Seokchan Song, Juhyoung Lee and Hoi-Jun Yoo; KAIST
VTA-NIC: Deep Learning Inference Serving in Network Interface Cards Kenji Tanaka, Yuki Arikawa, Kazutaka Morita, Tsuyoshi Ito, Takashi Uchida, Natsuko Saito, Shinya Kaji and Takeshi Sakamoto; NTT Device Technology Labs, NTT Corporation
A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA Using Non-Linear Neural Network Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada and Tadahiro Kuroda; The University of Tokyo
Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim and Hoi-Jun Yoo; KAIST
System architecture and software stack for GDDR6-AiM, SK hynix’s very first GDDR6- based Accelerator-in-Memory (AiM) Yongkee Kwon, Kornijcuk Vladimir, Nahsung Kim, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Guhyun Kim, Byeongju An, Jeongbin Kim, Jaewook Lee, Ilkon Kim, Jaehan Park, Chanwook Park, Yosub Song, Byeongsu Yang, Hyungdeok Lee, Seho Kim, Daehan Kwon, Seongju Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dongyoon Ka, Kyudong Hwang, Jeongje Park, Kyeongpil Kang, Jungyeon Kim, Junyeol Jeon, Myeongjun Lee, Minyoung Shin, Minhwan Shin, Jaekyung Cha, Changson Jung, Kijoon Chang, Chunseok Jeong, Euicheol Lim, Il Park and Junhyun Chun; SK hynix
Vision Perception Unit: Next-Generation Smart CMOS Image Sensor Wenqi Ji, Yubin Hu, Futang Wang, Yuze He, Xi Li, Jun Zhang, Yuxing Han and Jiangtao Wen; Tsinghua University
Large-scale Graph Neural Network Services through Computational SSD and In-Storage Processing Architectures Miryeong Kwon, Donghyun Gouk, Sangwon Lee and Myoungsoo Jung; KAIST
Trinity: End-to-End In-Database Near-Data Machine Learning Acceleration Platform for Advanced Data Analytics Ji-Hoon Kim, Seunghee Han, Kwanghyun Park, Soo-Young Ji and Joo-Young Kim; KAIST
DFX: A Low-latency Multi-FPGA Appliance for Accelerating Transformer-based Text Generation Seongmin Hong, Seungjae Moon, Junsoo Kim, Sungjae Lee, Minsub Kim, Dongsoo Lee and Joo-Young Kim; KAIST
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada and Tadahiro Kuroda; The University of Tokyo
LightTrader: World’s first AI-enabled High-Frequency Trading Solution with 16 TFLOPS / 64 TOPS Deep Learning Inference Accelerators Hyunsung Kim, Sungyeob Yoo, Jaewan Bae, Kyeongryeol Bong, Yoonho Boo, Karim Charfi, Hyo-Eun Kim, Hyun Suk Kim, Jinseok Kim, Byungjae Lee, Jaehwan Lee, Myeongbo Shim, Sungho Shin, Jeong Seok Woo, Joo-Young Kim, Sunghyun Park, and Jinwook Oh; Rebellions Inc.
Accelerating Graphic Rendering on Programmable RISC-V GPUs Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young and Hyesoon Kim; Georgia Tech
From High-Level Frameworks to custom Silicon with SODA Serena Curzel, Nicolas Bohm Agostini, Reece Neff, Ankur Limaye, Jeff (Jun) Zhang, Vinay Amatya, Marco Minutoli, Vito Giovanni Castellana, Joseph Manzano, David Brooks, Gu-Yeon Wei, Fabrizio Ferrandi and Antonino Tumeo; Politecnico di Milano
An Energy-efficient High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache Subsystem Zhiyong Li, Sangjin Kim, Dongseok Im, Donghyeon Han and Hoi-Jun Yoo; KAIST
Noema: Massive-Scale, Untethered, Real-Time Brain Activity Decoding Ameer Abdelhadi, Eugene Sha and Andreas Moshovos; University of Toronto